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Variable Latency Speculative Han Carlson Adder
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Variable Latency Speculative Han-Carlson Adder

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL13


Project Abstract

In this paper, we made an analysis on the logic operations involved in conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA to study the data-dependency and to identify redundant logic operations. We have eliminated all the redundant logic operations present in conventional CSLA and proposed a new logic formulation

for CSLA. In the proposed scheme, the carry-select operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit-patterns of two anticipating

carry-words (corresponding to Cin=0 and 1) and fixed Cin bits are used for logic optimization of carry select and generation units. An efficient CSLA design is obtained using optimized logic units. The proposed CSLA design involves significantly less area and delay than the recently proposed BEC-based CSLA. Due to small carry-output delay, the proposed CSLA design is a good candidate for square-root (SQRT)-CSLA. Theoretical estimate shows that the proposed SQRT-CSLA involves nearly 35% less area-delay-product (ADP) than the BEC-based SQRTCSLA which is the best amongst the existing SQRT-CSLA designs on average for different bit-widths. ASIC synthesis result shows that, the BEC-based SQRT-CSLA design involves 48% more ADP and consumes 50% more energy than the proposed SQRT-CSLA on average for different bit-widths.

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

·         Conventional CSLA is a RCA-RCA configuration which generates a pair of sum words and output-carry bits corresponding the anticipated input-carry  (cin= 0 and 1), and selects one out of each pair for final-sum and final-output-carry.

·         Conventional CSLA has less CPD than RCA, but the design is not attractive, since it uses dual RCA. Few attempt have been made to avoid dual use of RCA in CSLA design.

PROPOSED CONCEPT:           

·         The CBL based CSLA of  involves significantly less logic resource than the conventional CSLA, but it has longer CPD which is almost equals to that of RCA. To overcome this problem, SQRT-CSLA based on CBL have been proposed.

·         We observe that, logic optimization largely depends on availability of redundant operations in the formulation, where adder delay mainly depends on data-dependency.

EXISTING TECHNIQUE:

·         Ripple Carry Adder

PROPOSED TECHNIQUE:

·         New Carry Select Adder

TECHNIQUE DEFINITION:

·         A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the succeeding next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage.

TECHNIQUE DEFINITION:

·         This technique is  used  for  the next stage of  the binary output.

DRAWBACKS:

·         More area overhead system

·         More power consumption

·         Low speed architecture

ADVANTAGES:

·         Less area overhead system

·         Less power consumption

·         High speed architecture


 
 
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