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Area Delay Efficient Binary Adders in QCA.
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Area-Delay Efficient Binary Adders in QCA.

Category : VLSI


Sub Category : QCA TECHNOLOGY


Project Code : ITVL23


Project Abstract

As transistors decrease in size more and more of them can be accommodated in a single die, thus increasing chip computational capabilities. However, transistors cannot get much smaller than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical limit, even though the design of logic modules in QCA is not always straightforward. In this brief, we propose a new adder that outperforms all state-of-the-art competitors and achieves the best area-delay tradeoff. The above advantages are obtained by using an overall area similar to the cheaper designs known in literature. The 16-bit, 32-bit and 64-bit version of the novel adder is implemented by verilog language and FPGA Spartan 3.

 
 

EXISTING SYSTEM

PROPOSED SYSTEM

 

EXISTING CONCEPT:

·         The Existing adder design follows that of a conventional ripple carry adder, but with a new layout optimized to QCA technology.

·         The proposed adder design shows that a very high delay can be obtained with an optimized layout. This is in contrast to the conventional ripple carry adder.

 

PROPOSED CONCEPT:

·         An innovative technique is presented to implement high-speed low-area adders in QCA. The CLA and parallel-prefix adders are here exploited for the realization of a novel 2-bit addition slice.

·         The latter allows the carry to be propagated through two subsequent bit-positions with the delay of just one majority gate (MG).  

 

EXISTING TECHNIQUE:

·         Normal QCA implementation

 

 

PROPOSED TECHNIQUE:

         QCA implementation with majority gate

 

 

TECHNIQUE DEFINITION:

·         In normal QCA implementation, the circuit design is very complex

 

TECHNIQUE DEFINITION:

·         This technique reduces the complexity

And also reduces the product cost.

 

 

DRAWBACKS:

·         Low operation speed and more Delay

·        Adders can be implemented in larger Area

 

ADVANTAGES:

 

         Area Efficient

         Delay Efficient

 


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