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Low Power Variation Tolerant Nonvolatile Lookup Table Design
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Low-Power Variation-Tolerant Nonvolatile Lookup Table Design

Category : VLSI


Sub Category : EDA TOOL(TANNER TOOL)


Project Code : ITVL30


Project Abstract

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. This brief introduces a low-power variation-tolerant nonvolatile lookup table (nvLUT) circuit to overcome the reliability issue. Because of large ROFF/RON, 1T1R RRAM cell provides sufficient sense margin as a configuration bit and a reference resistor. A single-stage sense amplifier with voltage clamp is employed to reduce the power and area without impairing the reliability. Matched reference path is proposed to reduce the parasitic RC mismatch for reliable sensing. Evaluation shows that 22% reduction in delay, 38% reduction in power, and the tolerance of variations of 2.5× typical RON or ROFF in reliability are achieved for proposed nvLUT with six inputs.

PROPOSED SYSTEM:

                    The input count can also be easily extended to six, which is prevailing in current main-stream FPGA products. The overall architecture of nvLUT consists of an SSAVC, a tree multiplexer (TMUX), an MRP, a RRAM slice, and a footer transistor. The RRAM slice constitutes of four 1T1R RRAM cells at the left for configuration and a dummy RRAM cell at the right-most as a reference resistor. The truth table is stored in the RRAM slice in the form of resistance state, ROFF or RON, which is different from the logic voltage in SRAM. For example, in order to program the nvLUT as a NOR gate, R0 should be programmed as RON denoting 1, while R1, R2, and R3 should be programmed as ROFF denoting 0. The inputs IN0 and IN1 select the corresponding RRAM cell through TMUX. To perform the operations of LUT, the sense amplifier is employed to convert the resistance state of RRAM cell into logic voltage. The function of footer transistor MF is to allow current to flow during sensing and it is closed during precharge to restrain leakage.
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