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Design and Analysis of Approximate Compressors for Multiplication
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Design and Analysis of Approximate Compressors for Multiplication

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL35


Project Abstract

Inexact (or approximate) computing is an attractive paradigm for digital processing. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier. These designs rely on different features of compression, such that imprecision in computation can meet with respect to circuit-based figures of merit of a design. Four different schemes for utilizing the proposed approximate compressors are proposed and analyzed for a Dadda multiplier. Extensive simulation results are provided and an application of the approximate multipliers to image processing is presented.

 

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

         The main goal of either multi-operand carry-save addition or parallel multiplication is to reduce n numbers to two numbers; therefore, n-2 compressors (or n-2 counters) have been widely used in computer arithmetic.

         An-2 compressor (Figure 1) is usually a slice of a circuit that reduces n numbers to two numbers when properly replicated.

PROPOSED CONCEPT:

         Two designs of an approximate compressor are proposed. Intuitively to design an approximate 4-2 compressor, it is possible to substitute the exact full-adder cells in Figure3 by an approximate full-adder cell.

         Two different designs are proposed next to reduce the error rate; these designs offer significant performance improvement compared to an exact compressor.

EXISTING TECHNIQUE:

         Exact Compressors

PROPOSED TECHNIQUE:

         Approximate Compressors

TECHNIQUE DEFINITION:

         In exact compressors the circuit design complexity is more, so latency also very high.

TECHNIQUE DEFINITION:

         This technique reduces delay, number of transistors and power consumption compared to existing.

DRAWBACKS:

         More transistors

         High latency

ADVANTAGES:

         Reduced number of transistors

         Faster

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