The feature size of any semiconductor technology is defined as ** the minimum length of the MOS transistor channel between the drain and the source**. The technology node has been scaling year by year. From early 2000s it has shrunk from 180nm to 22nm designs today (2014).

You would have probably noticed that the technology scaling has followed:

**180nm -->> 130nm -->> 90nm -->> 65nm -->> 40nm -->> 28nm --> 22nm...**

Ever wondered who decides these numbers? Are these arbitrary or there's some inherent logic behind these numbers? Let's see.

In early 1970s, Gordon Moore of Intel Corp. predicted that the number of transistor on a an integrated circuit would double itself in approximately 18-24 months. This prediction has proven to be accurate as scaling of technology continues unabated even after 40 years! Well, it's mainly because Moore's law has set out a challenge and a roadmap for designers to keep the scaling going!

You might ask yourself, why scaling? Here's why:

- If double number of transistors can be incorporated on the same area, it means we get double (roughly) functionality for the same cost!
- Alternatively, with scaling of technology, the same functionality will be available at roughly half the cost!
- Moreover, smaller the channel length, faster would be the transient response of the transistors which would translate into better performance!

The goal of every design company now is to double the number of transistors on their integrated circuits with each technology. As you would notice, the numbers above from 180nm to 130nm to 90nm scale down by roughly a factor of 0.7. What's so special about 0.7?

If the feature size of the transistor is scaled by 0.7, the area would be scaled by a factor of 0.7^{2}**=0.49 =~ 0.5**. That means if we scale our feature sizes by a factor of roughly 0.7, we would be able to pack twice the number of transistors on the same area as the previous technology