Low Power, Delay Optimized Buffer Design CMOS Technology

By Admin on


            Power dissipation and propagation delay in CMOS buffers driving large capacitive loads and proposes a  CMOS buffer design for improving power dissipation at optimized propagation delay. The reduction in power dissipation is achieved by minimizing short circuit power and subthreshold leakage power which is predominant when supply voltage (VDD) and threshold voltage (Vth) are scaled for low voltage applications in deep sub micron (DSM) region.

           Large capacitive loads are often present in CMOS integrated circuits and tapered buffers are used to drive these large capacitive loads at high speed, while ensuring that the load placed on previous stages of the signal path is not too large.These buffers are used in the memory access path as word-line drivers, to drive large off-chip capacitances in I/O circuits, and in clock trees to ensure that skew constraints are satisfied. But,deployment of these buffers in high-performance systems imposes a power overhead on each instance regardless to its actual performance.High-performance VLSI design is attracting much attention because of emerging need for miniaturization, and hence design optimization for trading-off power and performance in nano meter scale integrated circuits is the need of the present scenario, which demands a decrease in both supply voltage VDD(to maintain low power dissipation) and threshold voltage Vth (to sustain propagation delay reduction), but the fact is that the decrease in Vth not only increases leakage power but also short circuit power. while working in nano scale technology the total power dissipation of clock.


--->The buffer consists of a chain of inverter stages where width of each MOS transistor in a stage is increased by a constant factor(called taper factor) than that of the transistors in the previous stage. 

--->The model is named as split capacitor model as output capacitance and input capacitance of each stage is modeled separately. The constant increase in width of transistors in each stage provides fixed ratio of output current drive to output capacitance and hence equal rise, fall, and delay times for each stage.

--->Design of taper buffer is based on analytical modeling of performance criteria and analyzing them individually with respect to the parameters like capacitive load dependent tapering factor and number of stages, which are the two primary variables in the design of tapered buffers for a specific application. 

--->The design we have presented uses two different conditions.

First condition is, when number of buffer stages are N=ND to achieve minimum propagation delay irrespective of power dissipation.

Second condition is, when number of buffer stages are N=Nopt to minimize cost function.

SPIRO Google Plus