VLSI Architecture Design for Emerging Digital Systems

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VLSI Architecture Design for Emerging Digital Systems


                Advanced VLSI architecture designs are required to further reduce power consumption, compress chip area, and speed up operating frequency for high performance integrated circuits. With time-to-market pressure and rising mask costs in the semiconductor industry, engineering change order (ECO) design methodology plays a main role in advanced chip design. Digital systems such as communication and multimedia applications demand for advanced VLSI architecture design methodologies so that low power consumption, small area overhead, high speed, and low cost can be achieved.

       This special issue is dedicated to aspects of VLSI architecture design and their applications. Special interest focuses on emerging digital systems. This special issue contains eight papers that focus on the power minimization design, efficient hardware Trojan detection, low-area Wallace multiplier, gate-level circuit reliability analysis, low power and high speed arithmetic circuits, power effective fractional-N-PLL frequency synthesizer, power-saving architecture for network on chip, and ECO design.

On-chip power minimization using serialization-widening with frequent value encoding:

           The authors address the problem of the high-power consumption of the on-chip data buses by exploring a new framework for memory data bus. In particular, serialization-widening (SW) of data bus with frequent value encoding (FVE) is proposed to minimize the power consumption of the on-chip cache data bus.

Efficient hardware trojan detection with differential cascade voltage switch logic

               The authors present to exploit the inherent feature of differential cascade voltage switch logic (DCVSL) to detect hardware trojans (HTs) at runtime. By examining special power characteristics of DCVSL systems upon HT insertion, the authors can detect HTs, even if the HT size is small. Simulation results show that the method achieves up to 100% HT detection rate. The evaluation on ISCAS benchmark circuits shows that the scheme obtains a HT detection rate in the range of 66% to 98%.

Gate-level circuit reliability analysis: a survey 

           The authors provide an overview of some typical methods for reliability analysis with special focus on gate-level circuits that are either large or small, with or without reconvergent fan-outs. It is intended to help the readers gain an insight into the reliability issues and their complexity as well as optional solutions. Understanding the reliability analysis is also a first step towards advanced circuit designs for improved reliability in the future research.


     Thus VLSI architecture emerging nowadays on DIGITAL system  depends mainly focusing  Area,Speed, and Power.

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