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Synthesis of Majority/Minority Logic Networks

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Synthesis of Majority/Minority Logic Networks

Category : VLSI

Sub Category : QCA TECHNOLOGY

Project Code : ITVL20

Project Abstract
As CMOS technology reaches its physical limits, new technologies such as quantum-dot cellular automata, single electron tunneling, and tunneling-phase logic are being proposed as alternatives to CMOS technology. These technologies use either majority or minority logic to implement logic functions. Existing majority/minority logic synthesis methods, based on three-feasible networks, often result in suboptimal solutions. In this paper, an efficient algorithm to find the minimal majority gate mapping, along with a majority expression look-up table (MLUT) is developed. Based on the MLUT, a comprehensive majority/minority logic synthesis technique is proposed. A redundancy removal method is also developed to further optimize the synthesized circuit. This technique makes effort toward achieving different optimization goals and results in fewer majority gates and fewer levels than previous methods. For the 29 MCNC benchmark circuits, when targeted to optimize the logic levels, there is an average reduction of 7.0% in the number of levels as well as 6.3% in the number of gates. For optimization targeted to reduce gate counts, there is an average reduction of 9.5% in the number of gates as well as 0.8% in the number of levels, as compared to the best available method.

EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

· Traditional logic reduction methods produce simplified expressions in the two standard forms: sum of products and product of sums.

· Existing logic synthesis methods that target CMOS technology are not efficient enough to take full advantage of majority gates.

PROPOSED CONCEPT:

An efficient algorithm to find the minimal majority gate mapping, along with a majority expression look-up table (MLUT) is developed.

A redundancy removal method is also developed to further optimize the synthesized circuit.

This technique makes effort toward achieving different optimization goals and results in fewer majority gates.

EXISTING TECHNIQUE:

· Based on three-feasible networks.

PROPOSED TECHNIQUE:

quantum-dot cellular automata

TECHNIQUE DEFENITION:

· This method often results in suboptimal solutions.

TECHNIQUE DEFENITION:

· Various types of QCA devices can be constructed using different physical cell arrangements.

DRAWBACKS:

· Complex design.

· Delay is high.

ADVANTAGES:

Decreased power consumption.

Delay is reduced.

MILE STONES

GUARANTEES

	So far we have provided R&D training for more than 1,00,000 engineering Students.
	Had conducted seminars in the recent trends of technology at various colleges.
	Our research projects had been presented in various National & International Conferences.
	Most of our projects were identified by the industries as suitable for their needs.
	Our n-number of students got research scholarship to extend our assisted projects for further development.

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	SPIRO guarantees quality instructors.
	SPIRO guarantees competence.
	SPIRO guarantees that training from SPIRO will be more cost-effective than training from any other source.
	SPIRO guarantees that students in open-enrollment classes are protected against cancellations and will be able to receive desired training at the cost they expect and in the time frame they have planned.
	SPIRO guarantees overall quality with a 100% money-back guarantee. If you're not totally satisfied for any reason, simply withdraw before the second day of any class. Notify the instructor and return all course materials and you will receive a 100% refund.

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For Project Enquiry +91 9962 067 067

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Project Zone > Electronics > VLSI

Synthesis of Majority/Minority Logic Networks

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A RESEARCH & DEVELOPMENT ORGANIZATION

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Project Zone > Electronics > VLSI

Synthesis of Majority/Minority Logic Networks

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Project Titles
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