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EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

         Despite the static power dissipation, the RSFQ logic has its undisputed advantages.

         One of the most attractive properties of RSFQ logic is its local timing.

        The clock pulses in RSFQ propagate together with data, making it attractive for high-speed architecture.

         The second feature is its dc power, that is obviously superior to ac-power driven logics, and, especially, to multiphase ac power.

PROPOSED  CONCEPT:

         The two versions of an 8-bit parallel adder employing a wave-pipelined architecture half-adder (HA) cells. The adders were constructed with an asynchronous carry.

         It is in sensitive to the delay between inputs, allowing high-throughput operation of the adder. The first design was a most straight-forward approach imposed by the aligned data front requirement.

         In this clock signal follows the data, resulting in a single clock operation. Clock is needed for producing the SUM (XOR) output, while the CARRY (AND) output signal is being generated and propagated asynchronously.

EXISTING TECHNIQUE:

         RSFQ (Rapid Single-Flux-Quantum) logic

PROPOSED TECHNIQUE:

        Ripple-carry 8-bit wave pipeline adder.

         “aligned-front” 8-bit wave pipeline adder.

EXISTING DEFINITION:

         The most attractive properties of RSFQ logic is its local timing. The clock pulses in RSFQ propagate together with data, making it attractive for high-speed.

         The second feature is its dc power that is obviously superior to ac-power driven logics.

PROPOSED DEFINITION:

·         The two techniques as same functions half adders only used to generate the output in the first technique 36 half adders are used and the carry from last adder are taken as output.

·         The second technique is same but carry of two adders are summed up and used as input.

DRAWBACKS:

         Static Power dissipation.

        Delay and Area high.

ADVANTAGES:

         Elimination of static power dissipation.

         Delay and Area Low.

         High speed process.