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PERFORMANCE-ORIENTED PARTITIONING FOR TASK SCHEDULING OF PARALLEL RECONFIGURABLE ARCHITECTURES

ABSTRACT

 In this paper we study about Parallel reconfigurable computing (PRC) architecture consists of multiple dynamic reconfigurable computing units. Parallel reconfiguration System, it needs to be partitioned such that each sub-circuit can be executed to the DRC units in a PRC system. For high performance, this paper proposes a greedy algorithm that maximizes data parallelism for task scheduling of parallel reconfigurable architectures with unlimited resources. The proposed algorithm generates an optimal solution in polynomial n time, where n is the total number of the tasks. After obtaining a depth optimal solution, we reduce the resources without decreasing performance by the duplication packing operations. The partitioning task is to determine task assignment on the RPUs but a task scheduling algorithm has to take task dependencies, data communication, and task resource utilization into account to fully exploit the performance of a PRC system.

EXISTING SYSTEM	PROPOSED SYSTEM
EXISTING CONCEPT:- In the existing system previous works is to minimize the resource costs but the objective of the works in this paper is to optimize performance the previous reconfigurable partitioning algorithms can be roughly divided into three classes. In the existing works an architecture consisting of reconfigurable processing units (RPUs) can further optimize system performance.	PROPOSED CONCEPT:-        In the proposed system we implement this paper proposes a greedy algorithm that maximizes data parallelism for task scheduling of parallel Reconfigurable architectures with   unlimited resources.   We can get System Performance and allocate the task using Reconfigurable architectures.
EXISTING TECHNIQUE:- Parallel processing technique	PROPOSED TECHNIQUE:- Directed Acyclic Graphs(DAGs)
TECHNIQUE DEFNITION:-   Parallel processing technique usually utilizes multiple instructions, multiple data (MIMD) architecture. The MIMD organization with multiple processors and I/O processors can access one or more memory module via bus. However, this kind of organization has a            problem	TECHNIQUE DEFNITION:-   Directed acyclic graphs (DAGs) are partitioned into five tasks. Each node represents an operator or a function. If the directed edges are assumed to represent the data dependency between the nodes of the graph.
DRAWBACKS:- It’s taken more time to complete the Process. We can’t Reconfiguration the System.	ADVANTAGES:- Reduce Time and Cost Find the Optimal Solution for Scheduling task in PRC.