For Project Enquiry +91 9962 067 067

EXISTING SYSTEM

PRPOSED SYSTEM

EXISTING CONCEPT:

            A CMOS  transistor (or device) has four terminals: gate, source , drain , and a fourth terminal that we shall ignore until the next section. A CMOS transistor is a switch. The switch must be conducting or on to allow current to flow between the source and drain terminals (using open and closed for switches is confusing—for the same reason we say a tap is on and not that it is closed ). The transistor source and drain terminals are equivalent as far as digital signals are concerned—we do not worry about labeling an electrical switch with two terminals.

PROPOSED SYSTEM:

           In adiabatic logic circuits, ramp type supply voltage is used to slow down the charge transport mechanism. Hence, the supply clock plays the pivotal role. A ramp type supply voltage φ(t) is considered in Fig. 1(a), which gradually swings in between logic 0 (Gnd potential) and logic 1 (VDD) in time duration 2T, where f (=1/2T ) is the supply clock’s frequency. The power supply waveform φ(t) can be divided into charging phase, when φ(t) ramps up from 0 to VDD in 0 to T unit time and discharging phase when φ(t) ramps down from VDD to 0 in T to 2T unit time.

EXISTING TECHNIQUE:

         Normal CMOS Logic

PROPOSED TECHNIQUE:

         SAL Adiabatic Logic

TECHNIQUE EXPLANATION:

       If Vin is down (0 volts), NFET is OFF and PFET is ON pulling V_out to V_dd (high = 1)

      If Vin is up (at Vdd), NFET is ON hard and PFET is OFF pulling V_out low to Gnd (“0”)

TECHNIQUE EXPLANATION:

                 The design as in SAL basic logic gates have been implemented using either the pull-up or the pull-down transistors. Therefore,

the SAL-based CLA is also area efficient in comparison with the conventional structure.

DRAWBACKS:

         Number of transistor large.

         Power is high

ADVANTAGES:

         Number of transistor less

         Power is less