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EXISTING SYSTEM

PROPOSED SYSTEM

EXISTING CONCEPT:

·         The negative bias temperature instability effect occurs when a pMOS transistor is under negative bias, increasing the threshold voltage of the pMOS transistor, and reducing multiplier speed.

·         A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is under positive bias. Both effects degrade transistor speed, and in the long term, the system may fail due to timing violations.

PROPOSED CONCEPT:

·         We propose an aging-aware reliable multiplier design with novel adaptive hold logic (AHL) circuit. The multiplier is based on the variable-latency technique

·         The AHL circuit to achieve reliable operation under the influence of NBTI and PBTI effects. Our proposed architecture with the 16×16 column-bypassing multipliers and row-bypassing multipliers.

EXISTING TECHNIQUE:

·         Variable-latency pipelined multiplier architecture with a Booth algorithm

PROPOSED TECHNIQUE:

·         Novel adaptive hold logic (AHL) circuit

TECHNIQUE DEFENITION:

·         These research designs were able to reduce the timing waste of traditional circuits to improve performance, but they did not consider the aging effect.      

TECHNIQUE DEFENITION:

·         The AHL circuit can decide whether the input patterns require one or two cycles and can adjust the judging criteria to ensure that there is minimum performance degradation after considerable aging occurs.

DRAWBACKS:

·         No improvements in Aging effect and performance degradation is more

·         More timing waste

ADVANTAGES:

         less performance degradation

         less timing waste