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Project Zone > Electronics > VLSI

Fault Tolerant Parallel Filters Based on Error Correction Codes

Category : VLSI


Sub Category : LOW POWER


Project Code : ITVL11


Project Desc : Digital filters are widely used in signal processing and communication systems. In some cases, the reliability of those systems is critical, and fault tolerant filter implementations are needed. Over the years, many techniques that exploit the filters structure and properties to achieve fault tolerance have been proposed.

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Variable Latency Speculative Han-Carlson Adder

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL13


Project Desc : In the proposed scheme, the carry-select operation is scheduled before the calculation of final-sum, which is different from the conventional approach. Bit-patterns of two anticipating carry-words (corresponding to Cin=0 and 1) and fixed Cin bits are used for logic optimization of carry select and generation units.

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A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL14


Project Desc : Several variable latency speculative adders, for various operand lengths, using both Han-Carlson and Kogge-Stone topology, have been synthesized using the UMC 65 nm library. Obtained results show that proposed variable latency Han-Carlson adder outperforms both previously proposed speculative Kogge-Stone architectures and non-speculative adders, when high-speed is required.

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Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n}

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL15


Project Desc : Transpose form finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that results in significant saving of computation. However, transpose form configuration does not directly support the block processing unlike direct form configuration.

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Energy-Efficient Approximate Multiplication for Digital Signal Processing and Classification Applications

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL16


Project Desc : First, a sign detection algorithm for the restricted moduli set is described. The new algorithm allows for parallel implementation and consists exclusively of modulo 2n additions. Then, a sign detection unit for the moduli set {2n+1 ? 1, 2n ? 1, 2n} is proposed based on the new sign detection algorithm.

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An Optimized Modified Booth Recoder for Efficient Design of the Add- Multiply Operator.

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL17


Project Desc : The need to support various digital signal processing (DSP) and classification applications on energy-constrained devices has steadily grown. Such applications often extensively perform matrix multiplications using fixed-point arithmetic while exhibiting tolerance for some computational errors. Hence, improving the energy efficiency of multiplications is critical

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Low-Latency Successive-Cancellation Polar Decoder Architectures Using 2-Bit Decoding.

Category : VLSI


Sub Category : HIGH SPEED


Project Code : ITVL18


Project Desc : We introduce a structured and efficient recoding technique and explore three different schemes by incorporating them in FAM designs. Comparing them with the FAM designs which use existing recoding schemes, the proposed technique yields considerable reductions in terms of critical delay, hardware complexity and power consumption of the FAM unit.

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Coplanar Full Adder in Quantum-Dot Cellular Automata via Clock-Zone-Based Crossover

Category : VLSI


Sub Category : QCA TECHNOLOGY


Project Code : ITVL19


Project Desc : In this paper, we present a novel reformulation for the last stage of SC decoding. The proposed reformulation leads to two benefits. First, critical path and hardware complexity in the last stage of SC algorithm is significantly reduced. Second, 2 bits can be decoded simultaneously instead of 1 bit.

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Synthesis of Majority/Minority Logic Networks

Category : VLSI


Sub Category : QCA TECHNOLOGY


Project Code : ITVL20


Project Desc : We use a coplanar QCA crossover architecture in the design of QCA full adders that leads to reduction of QCA cell count and area consumption without any latency penalty. We further investigate the impact of these gains on carry flow QCA adders.

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Design and simulation of Turbo encoder in quantum-dot cellular automata

Category : VLSI


Sub Category : QCA TECHNOLOGY


Project Code : ITVL21


Project Desc : As CMOS technology reaches its physical limits, new technologies such as quantum-dot cellular automata, single electron tunneling, and tunneling-phase logic are being proposed as alternatives to CMOS technology.

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