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Project Zone > Electronics > VLSI

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

Category : VLSI


Sub Category : EDA TOOL(TANNER TOOL)


Project Code : ITVL32


Project Desc : This paper deals with: 1) the design and implementation of a universal set of IC gates, CMOS 0.35 ?m technology, that carry out extended AND operators: eAND1, eAND2, eAND3, Successor (SUC), and Maximum (MAX) operators to perform synthesis of any MVL digital circuits; and 2) the synthesis of an MVL multiplexer and latch memory circuits.

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Universal Set of CMOS Gates for the Synthesis of Multiple Valued Logic Digital Circuits

Category : VLSI


Sub Category : EDA TOOL(TANNER TOOL)


Project Code : ITVL33


Project Desc : Inexact (or approximate) computing is an attractive paradigm for digital processing. Inexact computing is particularly interesting for computer arithmetic designs. This paper deals with the analysis and design of two new approximate 4-2 compressors for utilization in a multiplier.

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A Generalized Algorithm and Reconfigurable Architecture for Efficient and Scalable Orthogonal Approximation of DCT

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL34


Project Desc : A simulation-based method requires both programming efforts and a time-consuming execution for evaluating the effect of errors. This method becomes particularly expensive when dealing with various sizes and types of approximate adders. In this paper, a framework based on analytical models is proposed for evaluating the error characteristics of approximate adders.

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Design and Analysis of Approximate Compressors for Multiplication

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL35


Project Desc : The increase in complexity also poses reliability challenges and creates the need for fault tolerant implementations. A scheme based on error correction coding has been recently proposed to protect parallel filters.

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An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL36


Project Desc : we design reconfigurable adder/subtractor blocks (RABs), which have the ability to modulate their degree of approximation, and subsequently integrate these blocks in the motion estimation and discrete cosine transform modules of the MPEG encoder.

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Efficient coding scheme for fault Tolerant parallel filter

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL37


Project Desc : we introduce a novel 8-point DCT approximation that requires only 14 addition operations and no multiplications. The proposed transform possesses low computational complexity and is compared to state-of-the-art DCT approximations in terms of both algorithm complexity and peak signal-to-noise ratio.

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Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL38


Project Desc : This paper proposes a low-cost high-throughput multi standard transform (MST) core.

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Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL39


Project Desc :

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High-Throughput Multi standard Transform Core Supporting MPEG /H.264/VC-1 Using Common Sharing Distributed Arithmetic

Category : VLSI


Sub Category : VLSI with MATLAB


Project Code : ITVL40


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